AIJobalert.comSarkari Naukri • Behtar Bhavishya

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AIJobalert.comSarkari Naukri • Behtar Bhavishya

Computer Organization and Architecture (Unit 1 Overview)

This lecture covers the foundational concepts of Computer Organization and Architecture, including functional units, bus structures, and bus arbitration techniques. It details register transfers, micro-operations, and memory transfer operations like read and write. Additionally, it explores CPU processor organization, instruction cycles, and diverse addressing modes used in assembly architecture.

Computer
English
· 7 topics
Checked against the video on 18 Oct 2026

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Computer Organization and Architecture (Unit 1 Overview)

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This lecture covers the foundational concepts of Computer Organization and Architecture, including functional units, bus structures, and bus arbitration techniques. It details register transfers, micro-operations, and memory transfer operations like read and write. Additionally, it explores CPU processor organization, instruction cycles, and diverse addressing modes used in assembly architecture.

Introduction to Computer Organization and Architecture

Computer Organization deals with how hardware components are connected and function internally to realize the architectural specifications.
Computer Architecture focuses on the attributes of a computer system visible to a programmer, such as instruction sets, data types, and addressing modes.
Must knowComputer Architecture defines what the computer does (programmer view), whereas Computer Organization focuses on how the computer performs it (hardware implementation).
The five primary functional units of a computer system are the input unit, memory unit, arithmetic and logic unit (ALU), control unit (CU), and output unit.
The Central Processing Unit (CPU) contains both the Arithmetic and Logic Unit (ALU) and the Control Unit (CU).
Control units are categorised mainly into two structural designs: hardwired control units and microprogrammed control units.

Basis	Computer Architecture	Computer Organization
Meaning	What computer does	How computer does
Focus	Programmer view	Hardware implementation
Related to	Instruction set, addressing	Hardware units, signals
Characteristic	Compatibility	Performance
Example	Instruction format	Cache memory design

Buses and Bus Architecture

A bus is a shared communication pathway consisting of parallel wires used to transmit signals among computer components like the CPU, memory, and I/O devices.
System buses are divided into three types: the Address Bus, the Data Bus, and the Control Bus.
Must knowThe address bus is strictly unidirectional from the CPU to memory and I/O ports, whereas the data bus and control bus are bidirectional.
An address bus of width n bits can address a total of 2ⁿ unique memory locations.
In a single-bus structure, all units share one bus, creating potential bus contention and limiting transfers to one at a time.
Multiple-bus structures provide separate paths (e.g., a dedicated memory bus), boosting processing speed at the cost of higher circuit complexity.

Bus Arbitration

Bus arbitration is the mechanism used to decide which requesting master device gets access to the shared bus at any given time.
The device currently granted bus control is referred to as the bus master.
In the daisy chaining method, a single bus grant signal passes serially from one device to the next; physical proximity to the controller determines priority.
In the polling or rotating priority method, a controller sends address lines to poll devices sequentially in a round-robin circular order.
In the independent request method, each bus master has its own dedicated bus request (BR) and bus grant (BG) lines connected to a priority decoder.
Must knowThe independent request method offers the fastest arbitration response time for high-speed systems, but requires the highest amount of hardware lines.

Registers and Register Transfer

Registers are small, ultra-fast storage elements internal to the CPU used to retain data, instructions, and addresses during processing.
General-purpose registers (such as R0 through R7) perform arbitrary storage and calculation tasks, while special-purpose registers perform dedicated architectural tasks.
The Accumulator (AC) stores intermediate calculation results and operands for the ALU.
The Program Counter (PC) holds the memory address of the next sequential instruction to be fetched and executed.
The Instruction Register (IR) holds the binary code of the instruction currently being executed by the processor.
Must knowThe Stack Pointer (SP) stores the memory address representing the top element of the execution stack.
Register Transfer Language (RTL) is a symbolic notation denoting micro-operations and data transfers between registers, written in the general form: Destination <- Source.

Bus Transfer and Memory Transfer

Transferring data between multiple registers via a common bus can be implemented using either multiplexers (MUX) or tri-state buffers.
For n-bit registers, exactly n multiplexers are required to construct a common bus system.
The number of selection lines needed for a common bus multiplexer system connecting k registers is determined by the formula: S = log2(k).
A tri-state buffer produces three operational output states: logic 0, logic 1, and a high-impedance (High-Z) open-circuit state.
A Memory Read operation requires loading the desired address into the Memory Address Register (MAR), asserting the Read control signal, and copying the received data from memory into the Memory Data Register (MDR).
A Memory Write operation loads the target address into the MAR, places the data into the MDR, and asserts the Write control line to commit the byte into memory.

Processor Organization and Instruction Cycle

Processor organization denotes the internal arrangement and coordination of the ALU, register files, and control unit.
Every instruction cycle consists of three continuous sequential phases: Fetch, Decode, and Execute.
In the Fetch phase, the address in the Program Counter is sent to MAR, data is transferred from memory to MDR, then into the IR, and finally PC increments (PC <- PC + 1).
Single accumulator organization utilizes one primary working register (AC) and mainly implements one-address instruction formats.
General register organization contains multiple general-purpose registers and supports two-address or three-address instruction formats.
Must knowStack organization uses a zero-address instruction format because operands are implicitly retrieved directly from the top of the stack.

Addressing Modes

An addressing mode specifies the rule or syntax used by the CPU to calculate the effective address of an operand during instruction execution.
Effective Address (EA) represents the actual physical memory address where the operand data is located.
In Immediate mode, the operand value is explicitly provided inside the instruction itself rather than at an address.
In Register Direct mode, the operand is located inside a specified CPU register, requiring zero memory access cycles.
In Register Indirect mode, the specified register contains the effective memory address of the operand.
Must knowIn Relative addressing mode, the effective address is computed by adding the address field of the instruction to the content of the Program Counter (EA = PC + Address).
Auto-increment mode uses the register content as the effective address first, and then automatically increments the register value by a constant step size.

Key terms

Computer Architecture: The logical design and functional behaviour of a computer system visible to the programmer.
Computer Organization: The operational structure and hardware interconnection of units realizing the architectural specification.
Bus Master: The specific device that currently controls and drives the system bus.
Effective Address: The exact memory address where an operand resides for execution.
High Impedance: An open-circuit output state of a tri-state buffer isolating a device from the shared bus.
Program Counter: A dedicated special-purpose register holding the memory address of the next instruction to execute.

Formulas

Addressable Locations = 2ⁿ: Calculates the maximum number of addressable locations given an address bus of n bits.
Number of Selection Lines = log2(k): Determines the number of select lines needed for a multiplexer or decoder serving k registers.
EA = PC + Address Field: Calculates the effective address in Relative Addressing Mode.
EA = Index Register + Address Field: Calculates the effective address in Indexed Addressing Mode.
EA = Base Register + Address Field: Calculates the effective address in Base Register Addressing Mode.

Quick revision

An address bus is strictly unidirectional, directed outward from the CPU.
A data bus is bidirectional because the CPU reads and writes memory data.
Daisy chaining prioritises bus requests based on physical closeness to the master controller.
For registers of n-bit length, a common bus requires exactly n multiplexers.
The Instruction Register holds the currently active executing instruction.
The Program Counter automatically increments after the fetch phase of an instruction.
Stack architectures operate on zero-address instructions due to implicit top-of-stack operands.
Immediate addressing involves zero memory access because the operand is in the instruction.

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